Memory device and manufacturing method for the same

ABSTRACT

A memory device and a manufacturing method for the same are provided. The memory device comprises a NAND memory string. The NAND memory string includes a U-shape channel, a first inversion gate electrode and a second inversion gate electrode. The U-shape channel includes a bottom channel surface, a first outer channel sidewall and a second outer channel sidewall. The bottom channel surface is between the first outer channel sidewall and the second outer channel sidewall opposing to the first outer channel sidewall. The first inversion gate electrode is electrically coupled to the U-shape channel and is disposed under bottom channel surface. The second inversion gate electrode is electrically coupled to the U-shape channel and is disposed outside the first outer channel sidewall, and separated from the first inversion gate electrode.

BACKGROUND Technical Field

The disclosure relates to a semiconductor device and a manufacturingmethod for the same, and particularly to a memory device and amanufacturing method for the same.

Description of the Related Art

As critical dimensions of devices in integrated circuits shrink towardperceived limits of manufacturing technologies, designers have beenlooking to techniques to achieve greater storage capacity, and toachieve lower costs per bit. Technologies being pursued include a NANDmemory and an operation performed therefor.

SUMMARY

The present disclosure relates to a memory device and a manufacturingmethod for the same.

According to an embodiment, a memory device is disclosed. The memorydevice comprises a NAND memory string. The NAND memory string comprisesa U-shape channel, a first inversion gate electrode and a secondinversion gate electrode. The U-shape channel UC comprises a bottomchannel surface, a first outer channel sidewall and a second outerchannel sidewall. The bottom channel surface is between the first outerchannel sidewall and the second outer channel sidewall opposing to thefirst outer channel sidewall. The first inversion gate electrode iselectrically coupled to the U-shape channel and is disposed on thebottom channel surface. The second inversion gate electrode iselectrically coupled to the U-shape channel and is disposed outside thefirst outer channel sidewall, and separated from the first inversiongate electrode.

According to another embodiment, a manufacturing method for a memorydevice is disclosed. The manufacturing method comprises the followingsteps. A first inversion gate electrode is formed by using a firstpatterning process. A first stack structure is formed by using a secondpatterning process after the first patterning process. The first stackstructure comprises gate electrode elements and insulating films stackedalternately. The gate electrode elements comprise a second inversiongate electrode. A channel element is formed on the first inversion gateelectrode and the second inversion gate electrode.

The above and other embodiments of the disclosure will become betterunderstood with regard to the following detailed description of thenon-limiting embodiment(s). The following description is made withreference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a cross-section view of a memory device according toa concept in an embodiment.

FIG. 1B is a schematic drawing of a circuit of the memory device in FIG.1A.

FIG. 2A illustrates a cross-section view of a memory device according toa concept in another embodiment.

FIG. 2B is a schematic drawing of a circuit of the memory device in FIG.2A.

FIG. 3A illustrates a cross-section view of a memory device according toa concept in yet another embodiment.

FIG. 3B is a schematic drawing of a circuit of the memory device in FIG.3A.

FIG. 4 illustrates a cross-section view of a memory device according toa concept in an embodiment.

FIG. 5A to FIG. 5H illustrate a manufacturing method for a memory deviceaccording to a concept in an embodiment.

FIG. 6 illustrates a step for a manufacturing method for a memory deviceaccording to a concept in an embodiment.

DETAILED DESCRIPTION

The illustrations may not be necessarily drawn to scale, and there maybe other embodiments of the present disclosure which are notspecifically illustrated. Thus, the specification and the drawings areto be regard as an illustrative sense rather than a restrictive sense.Moreover, the descriptions disclosed in the embodiments of thedisclosure such as detailed construction, manufacturing steps andmaterial selections are for illustration only, not for limiting thescope of protection of the disclosure. The steps and elements in detailsof the embodiments could be modified or changed according to the actualneeds of the practical applications. The disclosure is not limited tothe descriptions of the embodiments. The illustration uses thesame/similar symbols to indicate the same/similar elements.

FIG. 1A and FIG. 1B are referred. FIG. 1A illustrates a cross-sectionview of a memory device according to a concept in an embodiment. FIG. 1Bis a schematic drawing of a circuit of the memory device. In anembodiment, the memory device is a NAND flash memory device having asingle gate vertical channel (SGVC) structure.

Referring to FIG. 1A, the memory device comprises a substrate 102, stackstructures, a dielectric layer 104, a channel element C and a firstinversion gate electrode IG1. The stack structures are on the substrate102. For example, the stack structures comprise a first stack structureK1, a second stack structure K2, a third stack structure K3, a fourthstack structure K4, etc., separated from each other. The dielectriclayer 104 may be formed on side walls and upper surfaces of the stackstructures and on the first inversion gate electrode IG1. A portion ofthe dielectric layer 104 on a sidewall surface KS1 of the first stackstructure K1, a sidewall surface KS2 of the second stack structure K2,and the upper surface (such as a top surface GTS) of the first inversiongate electrode IG1 has a U shape. The channel element C is formed overthe dielectric layer 104. The channel element C comprises a U-shapechannel UC on the sidewall surface KS1 of the first stack structure K1,the sidewall surface KS2 of the second stack structure K2, and the uppersurface (such as the top surface GTS) of the first inversion gateelectrode IG1.

Each of the stack structures may comprise gate electrode elements andinsulating films stacked alternately. The gate electrode elements of astack structure may comprise a bottom gate electrode element EB, a topgate electrode element ET, and intermediate gate electrode elements EMbetween the bottom gate electrode element EB and the top gate electrodeelement ET. The insulating films of a stack structures may comprisebottom insulating layer IB, a top insulating film IT, and intermediateinsulating films IM between the insulating layer IB and the insulatingfilm IT. In an embodiment, for example, for the first stack structureK1, the bottom gate electrode element EB may be functioned as a secondinversion gate electrode IG2, the top gate electrode element ET may beused as a selection line such as a ground selection line GSL, and theother intermediate gate electrode elements EM may be used as word linesWL. For the second stack structure K2, the bottom gate electrode elementEB may be used as a third inversion gate electrode IG3, the top gateelectrode element ET may be used as a selection line such as a stringselection line SSL, and the other intermediate gate electrode elementsEM may be used as word lines WL. The first inversion gate electrode IG1and the second inversion gate electrode IG2 may be separated from eachother by the insulating layer IB of the first stack structure K1. Thefirst inversion gate electrode IG1 and the third inversion gateelectrode IG3 may be separated from each other by the insulating layerIB of the second stack structure K2.

Referring to FIG. 1A and FIG. 1B, the memory device comprises NANDmemory strings, and comprises memory units M defined between the U-shapechannel UC and the gate electrode elements EM used as the word lines WL.For example, the memory units M comprise memory units M1 and memoryunits M2 of a NAND memory string 108A. The memory units M1 of the NANDmemory string 108A are defined between the gate electrode elements EM ofthe first stack structure K1 and the U-shape channel UC. The memoryunits M2 of the NAND memory string 108A are defined between the gateelectrode elements EM of the second stack structure K2 and the U-shapechannel UC. In other words, the memory cells M of the NAND memory string108A comprise the memory cells M1 on the sidewall surface KS1 of thefirst stack structure K1, and the memory cells M2 on the sidewallsurface KS2 of the second stack structure K2. The other NAND memorystrings may are analogous to the NAND memory string 108A. For example, aNAND memory string 108B may comprise the memory units M defined on asidewall surface KS3 of the first stack structure K1 and a sidewallsurface KS4 of the third stack structure K3. A NAND memory string 108Cmay comprise the memory units M defined on a sidewall surface KS5 of thesecond stack structure K2 and a sidewall surface KS6 of the fourth stackstructure K4, and so on.

The U-shape channel UC may comprise a bottom channel surface CS1, afirst outer channel sidewall CS2 and a second outer channel sidewallCS3. The bottom channel surface CS1 is between the first outer channelsidewall CS2 and the second outer channel sidewall CS3 opposing to thefirst outer channel sidewall CS2. As shown in FIG. 1A, the bottomchannel surface CS1 of the U-shape channel UC faces toward the substrate102 (or the first inversion gate electrode IG1) The first inversion gateelectrode IG1 is under the dielectric layer 104 under the bottom channelsurface CS1. The first stack structure K1, comprising the groundselection line GSL, the word lines WL, and the second inversion gateelectrode IG2, is outside the bottom channel surface CS2 of the U-shapechannel UC. The second stack structure K2, comprising the stringselection line SSL, the word lines WL, and the third inversion gateelectrode IG3, is outside the second outer channel sidewall CS3 of theU-shape channel UC. The channel element C may be continuously extendedfrom an upper surface of the first stack structure K1, through the firstinversion gate electrode IG1, to be onto an upper surface of the secondstack structure K2. In other words, the U-shape channel UC may beextended beyond opposing upper and lower surfaces of each of the gateelectrode element EB, the gate electrode element ET, the gate electrodeelements EM (comprising the ground selection line GSL, the word linesWL, the second inversion gate electrode IG2, the third inversion gateelectrode IG3 and the string selection line SSL) of the first stackstructure K1 and the second stack structure K2.

Conductive elements are on the channel element C on the upper surfacesof the stack structures. For example, a conductive element 126A is onthe channel element C on the upper surface of the first stack structureK1. The conductive element 126A may be used as a common source line CSL.A conductive element 126B and a conductive element 126C are on thechannel element C on the upper surface of the second stack structure K2,and are separated from each other. The conductive element 126B and theconductive element 126C may be used as bit lines BL respectively fordifferent NAND memory strings.

Referring to FIG. 1A and FIG. 1B, the first inversion gate electrode IG1is electrically connected to a portion of the U-shape channel UC betweenthe second inversion gate electrode IG2 and the third inversion gateelectrode IG3. The first inversion gate electrode IG1, the secondinversion gate electrode IG2 and the third inversion gate electrode IG3are electrically connected to a portion of the U-shape channel UCbetween the memory cells M1 on the sidewall surface KS1 of the firststack structure K1 and the memory cells M2 on the sidewall surface KS2of the second stack structure K2.

Referring to FIG. 1A and FIG. 1B, in this embodiment, the first stackstructure K1, the second stack structure K2, the third stack structureK3 and the fourth stack structure K4, and the dielectric layer 104 andthe channel element C on the foregoing stack structures are disposed onthe first inversion gate electrode IG1. Therefore, U-shape channels UCof the NAND memory string 108A, the NAND memory string 108B, and theNAND memory string 108C are electrically connected to a commonly usedfirst inversion gate electrode IG1. In other words, in this embodiment,three NAND memory strings may be electrically connected a commonly usedfirst inversion gate electrode IG1. In addition, in an erasing step forthe memory device, the three NAND memory strings may be erased at thesame time as a block unit. In embodiment, for example in a readoperating step for the memory device, an inversion region may be inducedin a lower portion of the U shape U-shape channel UC of the NAND memorystring adjacent to the first inversion gate electrode IG1, the secondinversion gate electrode IG2 and the third inversion gate electrode IG3by applying voltages to the first inversion gate electrode IG1, thesecond inversion gate electrode IG2 and the third inversion gateelectrode IG3 to increase charge carrier concentration in the inversionregion. By which a resistance in a current path in the lower portion ofthe U-shape channel UC (or a resistance of the bit line BL) in anon-state of the memory device may be reduced. Therefore, a conductivitycharacteristic between opposing ends of the NAND memory string may beincreased. The circuit for the other NAND memory strings may beunderstood according to the similar concepts.

FIG. 2A and FIG. 2B are referred. FIG. 2A illustrates a cross-sectionview of a memory device according to a concept in another embodiment.FIG. 2B is a schematic drawing of a circuit of the memory device. Thememory device referred to FIG. 2A and FIG. 2B is different from thememory device referred to FIG. 1A and FIG. 1B as the followingdescription. In this embodiment, the first stack structure K1, and thedielectric layer 104 and the channel element C on the first stackstructure K1, the second stack structure K2, and the third stackstructure K3 are disposed on the first inversion gate electrode IG1.Therefore, U-shape channels UC of the NAND memory string 108A and theNAND memory string 108B are electrically connected to a commonly usedfirst inversion gate electrode IG1. The circuit for the other NANDmemory strings may be understood according to the similar concepts. Forexample, a NAND memory string 108D comprises the memory units M definedon a sidewall surface KS7 of the fourth stack structure K4 and definedon a sidewall surface KS8 of a fifth stack structure K5. The U-shapechannels UC of the NAND memory string 108C and the NAND memory string108D are electrically connected to another commonly used first inversiongate electrode IG1′. In other words, in this embodiment, two NAND memorystrings may be electrically connected a commonly used first inversiongate electrode IG1. In addition, in an erasing step for the memorydevice, the two NAND memory strings may be erased at the same time as ablock unit.

FIG. 3A and FIG. 3B are referred. FIG. 3A illustrates a cross-sectionview of a memory device according to a concept in yet anotherembodiment. FIG. 3B is a schematic drawing of a circuit of the memorydevice. The memory device referred to FIG. 3A and FIG. 3B is differentfrom the memory device referred to FIG. 1A and FIG. 1B as the followingdescription. The dielectric layer 104 and the U-shape channel UC betweenthe first stack structure K1 and the second stack structure K2 may bedisposed on the first inversion gate electrode IG1. In other words, theU-shape channel UC of the NAND memory string 108A is electricallyconnected to the first inversion gate electrode IG1. The circuit for theother NAND memory strings may be understood according to the similarconcepts. For example, the U-shape channel UC of the NAND memory string108B is electrically connected to the another first inversion gateelectrode IG1′, and the U-shape channel UC of the NAND memory string108C is electrically connected to yet another first inversion gateelectrode IG1″, and so on. In an embodiment, the first inversion gateelectrode IG1, the first inversion gate electrode IG1′ and the firstinversion gate electrode IG1″ may be respectively electrically connectedto voltage bias controlled independently. In other words, in thisembodiment, the NAND memory strings may be electrically connected to therespective first inversion gate electrodes IG1, and the memory devicemay be erased with one of the NAND memory strings as one basic unit. Inanother embodiment, the first inversion gate electrode IG1, the firstinversion gate electrode IG1′ and the first inversion gate electrodeIG1″ separated from each other may be electrically connected to a commonvoltage through conductive elements.

In other embodiments, other amounts (for example an amount of 16, butnot limited thereto) or combinations of the NAND memory strings may beelectrically connected to a commonly used first inversion gate electrodeIG1. In addition, the memory device may be erased with the NAND memorystrings electrically connected the commonly used first inversion gateelectrode IG1 as a basic block unit.

FIG. 4 illustrates a cross-section view of a memory device according toa concept in an embodiment, which is different from the memory devicereferred to FIG. 1A as the following description. In this embodiment,the dielectric layer 104 is extended beyond the top surface GTS of thefirst inversion gate electrode IG1 and is embedded into the firstinversion gate electrode IG1. Therefore, the dielectric layer 104 isadjoined with an electrode surface GS1, an electrode surface GS2, and anelectrode surface GS3 of the first inversion gate electrode IG1. Thesimilar concepts may be applied in embodiments illustrated withreferring to FIG. 2A and FIG. 3A, and so on.

FIG. 5A to FIG. 5H illustrate a manufacturing method for a memory deviceaccording to a concept in an embodiment.

Referring to FIG. 5A, an electrode layer 512 is formed on the substrate102. In an embodiment, the substrate 102 may comprise an insulatingmaterial, and the insulating may be formed on a semiconductor substrate.The semiconductor substrate comprises a silicon substrate, for example.In an embodiment, the insulating material may comprise an oxide, such assilicon oxide, and the like. The electrode layer 512 may comprise aconductive material, such as polysilicon, or a metal such as W, and soon. The electrode layer 512 may be formed by a deposition method such asa chemical vapor deposition method, a physical vapor deposition method,or other suitable methods.

Referring to FIG. 5B, a patterning process may be performed to theelectrode layer 512 to form the first inversion gate electrodes IG1separated from each other. The first inversion gate electrodes IG1 maybe separated by an hole 514 formed by an etching step removing a portionof the electrode layer 512. The insulating layer IB may be formed tofill the hole 514 and on the upper surface of the first inversion gateelectrode IG1. In an embodiment, the insulating layer IB may comprise anoxide such as silicon oxide. The insulating layer IB may be formed by adeposition method such as a chemical vapor deposition method, a physicalvapor deposition method, or other suitable methods.

Referring to FIG. 5C, gate electrode elements 516 and insulating films518 are stacked alternately on the insulating layer IB to form a stackstructure 520. The insulating films 518 may comprise an oxide such assilicon oxide, or a nitride such as silicon nitride, and so on. In anembodiment, for example, the insulating films 518 may comprise a topinsulating film 518T comprising a first insulating portion 518A and asecond insulating portion 518B on the first insulating portion 518A. Thefirst insulating portion 518A may comprise silicon oxide, and the secondinsulating portion 518B may comprise silicon nitride. The otherinsulating films 518 under the insulating film 518T may comprise siliconoxide. The gate electrode elements 516 may comprise a conductivematerial, such as polysilicon, or a metal such as W, etc. The gateelectrode elements 516 may be formed by a deposition method such as achemical vapor deposition method, a physical vapor deposition method, orother suitable methods.

Referring to FIG. 5D, a patterning process may be performed to the stackstructure 520 to form the stack structures at the same time. Forexample, the stack structure comprises the first stack structure K1, thesecond stack structure K2, etc. The stack structure, such as the firststack structure K1 and the second stack structure K2 may be separatedfrom each other by an opening 522 formed by an etching step of thepatterning process removing a portion of the stack structure 520. In anembodiment, for example, a hard mask layer 519 may be formed on thestack structure 520, and the patterning process may comprise forming apatterned photoresist (not shown) on the hard mask layer 519 by using alithographic etching process, transferring a pattern of the photoresistdown into the hard mask layer 519, and then transferring the pattern ofthe hard mask layer 519 down into the stack structure 520. Thepatterning process of other suitable methods may be also used. In thisembodiment, the etching step of the patterning process may use the firstinversion gate electrode IG1 as an etching stop layer. In an embodiment,the etching step may stop at the timing detecting a signal of the firstinversion gate electrode IG1 so as to form the opening 522 substantiallythe top surface GTS of the first inversion gate electrode IG1. Theopening 522 also exposes sidewall surfaces of the insulating films andthe gate electrode elements of each of the stack structures. The hardmask layer 519 may be removed after the patterning process.

Referring to FIG. 5E, the dielectric layer 104 is formed on the firstinversion gate electrodes IG1 and the stack structures exposed by theopening 522. In an embodiment, the dielectric layer 104 may comprise amultilayer structure of oxide-nitride-oxide (ONO). In anotherembodiment, the dielectric layer 104 may comprise a multilayer structureof oxide-nitride-oxide-nitride-oxide (ONONO). The channel element C isformed on the dielectric layer 104. For example, the channel element Ccomprises a semiconductor material, such as a doped polysiliconmaterial. The dielectric layer 104 and the channel element C may beformed by a deposition method such as a chemical vapor depositionmethod, a physical vapor deposition method, or other suitable methods.In other embodiments, the dielectric layer 104/the channel element C maybe formed with other suitable materials/structure, and/or methods.Portions of the dielectric layer 104 and the channel element C in theopening 522 have a U shape. That is, the portion of the channel elementC in the opening 522 is the U-shape channel UC.

Referring to FIG. 5F, an insulating material 524 is formed on thechannel element C. The insulating material 524 may comprise an oxidesuch as silicon oxide, or other suitable insulating materials.

Referring to FIG. 5G, conductive elements are formed on the channelelement C on the upper surfaces of the stack structures. For example,the conductive element 126A is formed on the channel element C on theupper surface of the first stack structure K1. The conductive element126B and the conductive element 126C are formed on the channel element Con the upper surface of the upper surface of the second stack structureK2. In an embodiment, the conductive elements may be formed by using alithographic etching step to remove a portion of the insulating material524 to form a via hole exposing the channel element C, filling the viahole with a conductive material, and then performing a CMP process toflatten the conductive material. The conductive material may comprise apolysilicon, a metal such as W, Cu, etc., or a metal silicide, and thelike.

Referring to FIG. 5H, a patterning process may be performed to form atrench 528 dividing channel element C into channel segmentscorresponding to the different NAND memory strings.

The manufacturing method for forming the memory device may be variedaccording to actual demands.

In an embodiment, for example, the step illustrated with FIG. 5G may bechanged to form a single conductive film (not shown) on the channelelement C on the upper surface of the first stack structure K1, and thenpattern the conductive film into the conductive element 126B and theconductive element 126C separated by the trench 528 as shown in FIG. 5H.

In another embodiment, the step illustrated with FIG. 5D may be replacedby a step illustrated with FIG. 6. In this embodiment, the etching stepof the patterning process may stop at a certain time after the timingdetecting the signal of the first inversion gate electrode IG1, withwhich the etching step may further proceed from the top surface GTS intoan inside portion of the first inversion gate electrode IG1. Therefore,an opening 622 substantially exposing the electrode surface GS1, theelectrode surface GS2, and the electrode surface GS3 of the firstinversion gate electrode IG1 is formed. In an embodiment, a thickness ofthe first inversion gate electrode IG1 may be larger than a thickness ofeach of the gate electrode elements of the stack structures, and thethickness of the first inversion gate electrode IG1 is sufficient toavoid etching through a whole thickness of the first inversion gateelectrode IG1 so as to ensure remain the first inversion gate electrodeIG1 under a lower surface of the U shape U-shape channel UC to provideeffect of reducing operating resistance of the memory device. Then, thestep as illustrated with FIG. 5E and the subsequent steps after FIG. 5may be performed to form the memory device as shown in FIG. 4, forexample.

While the disclosure has been described by way of example and in termsof the exemplary embodiment(s), it is to be understood that thedisclosure is not limited thereto. On the contrary, it is intended tocover various modifications and similar arrangements and procedures, andthe scope of the appended claims therefore should be accorded thebroadest interpretation so as to encompass all such modifications andsimilar arrangements and procedures.

1. A memory device, comprising a NAND memory string, the NAND memorystring comprising: a U-shape channel comprising a bottom channelsurface, a first outer channel sidewall and a second outer channelsidewall, the bottom channel surface being between the first outerchannel sidewall and the second outer channel sidewall opposing to thefirst outer channel sidewall; a first inversion gate electrodeelectrically coupled to the U-shape channel and disposed under thebottom channel surface; and a second inversion gate electrodeelectrically coupled to the U-shape channel and disposed outside thefirst outer channel sidewall, and separated from the first inversiongate electrode.
 2. The memory device according to claim 1, comprising afirst stack structure, wherein the first stack structure comprises gateelectrode elements and insulating films stacked alternately, the NANDmemory string comprises memory cells defined between the gate electrodeelements and the U-shape channel, wherein the second inversion gateelectrode is electrically connected to a portion of the U-shape channelbetween the first inversion gate electrode and the memory cells.
 3. Thememory device according to claim 2, further comprising second stackstructure, wherein the second stack structure comprises additional gateelectrode elements and additional insulating films stacked alternately,wherein additional memory cells are defined between the additional gateelectrode elements and the U-shape channel, wherein the first inversiongate electrode and the second inversion gate electrode are electricallyconnected to a portion of the U-shape channel between the memory cellsand the additional memory cells.
 4. The memory device according to claim3, wherein the NAND memory string further comprises the additionalmemory cells.
 5. The memory device according to claim 1, wherein theU-shape channel is extended beyond opposing surfaces of the secondinversion gate electrode.
 6. The memory device according to claim 1,further comprising an insulating layer, wherein the first inversion gateelectrode and the second inversion gate electrode are separated fromeach other by the insulating layer.
 7. The memory device according toclaim 1, further comprising a dielectric layer between the U-shapechannel and the first inversion gate electrode, and adjoined with thefirst inversion gate electrode.
 8. The memory device according to claim1, further comprising a third inversion gate electrode electricallycoupled to the U-shape channel and disposed outside the second outerchannel sidewall of the U-shape channel.
 9. The memory device accordingto claim 8, wherein the U-shape channel is extended beyond opposingsurfaces of the third inversion gate electrode.
 10. The memory deviceaccording to claim 8, wherein the first inversion gate electrode isseparated from the third inversion gate electrode.
 11. The memory deviceaccording to claim 8, comprising a first stack structure, the firststack structure comprises gate electrode elements and insulating filmsstacked alternately, the NAND memory string comprises memory cellsdefined between the gate electrode elements and the U-shape channel,wherein the first inversion gate electrode and the second inversion gateelectrode are electrically connected to a portion of the U-shape channelbetween the memory cells and the third inversion gate electrode.
 12. Thememory device according to claim 11, further comprising a second stackstructure, wherein the second stack structure comprises additional gateelectrode elements and additional insulating films stacked alternately,wherein additional memory cells are defined between the additional gateelectrode elements and the U-shape channel, wherein the first inversiongate electrode, the second inversion gate electrode and the thirdinversion gate electrode are electrically connected to a portion of theU-shape channel between the memory cells and the additional memorycells.
 13. A manufacturing method for a memory device, comprising:forming a first inversion gate electrode by using a first patterningprocess; forming a first stack structure by using a second patterningprocess after the first patterning process, wherein the first stackstructure comprises gate electrode elements and insulating films stackedalternately, the gate electrode elements comprise a second inversiongate electrode; and forming a channel element on the first inversiongate electrode and the second inversion gate electrode.
 14. Themanufacturing method for the memory device according to claim 13,further comprising forming a second stack structure, wherein the firststack structure and the second stack structure are formed at the sametime, and the second stack structure comprises additional gate electrodeelements and additional insulating films stacked alternately, theadditional gate electrode elements comprise a third inversion gateelectrode.
 15. The manufacturing method for the memory device accordingto claim 13, wherein an opening is formed through the second patterningprocess, the second inversion gate electrode has only a sidewall surfaceexposed by the opening.
 16. The manufacturing method for the memorydevice according to claim 13, wherein an opening is formed by the secondpatterning process, and the first inversion gate electrode is exposed bythe opening.
 17. The manufacturing method for the memory deviceaccording to claim 16, wherein the first inversion gate electrode hasonly a top surface exposed by the opening.
 18. The manufacturing methodfor the memory device according to claim 16, wherein an upper surfaceand a sidewall surface of the first inversion gate electrode are exposedby the opening.
 19. The manufacturing method for the memory deviceaccording to claim 16, wherein the channel element is formed in theopening.
 20. The manufacturing method for the memory device according toclaim 13, further comprising forming a dielectric layer on the firstinversion gate electrode and the second inversion gate electrode,wherein the channel element is formed on the dielectric layer.